Super-regenerative receivers are widely used in variety of applications including low-power short-range RF links. Such applications require low-cost receiver with extremely low power consumption. Super-regenerative receiver is suitable for such applications due to its simplicity and relatively good sensitivity. Frequency instability is well known disadvantage of super-regenerative receiver. Therefore, phase-locked loop has been suggested as a means for precise frequency stabilization. One such super-regenerative receiver design is described in Norbert Joehl, et al. “A Low-Power 1-GHz Super-Regenerative Transceiver with Time-Shared PLL Control” IEEE Journal of Solid-State Circuits, vol. 36, No.7, July 2001, which is incorporated here by reference. At least three additional blocks are required (ECL frequency divider, sequential phase comparator and charge pump) for such super-regenerative receiver configuration; thus the cost of receiver is increased. FIG. 1 is a block diagram of such prior art super-regenerative receiver.
Referring now to FIG. 1, a prior art super-regenerative receiver includes a voltage-controlled oscillator (VCO) 104 which is pulsed ON and OFF (quenched) by a quench signal 176 and is responsive to both frequency control signal 174 and amplitude control signal 158. Low-noise amplifier 102, which amplifies received RF input signal 150 to produce amplified RF signal 152, is connected between antenna 100 (or other equivalent source of RF input signal) and voltage-controlled oscillator 104. Low-noise-amplifier 102 also provides reverse isolation to the antenna, thus minimizing the re-radiation of the receiver's own oscillator energy and preventing interference to other receivers in the vicinity. An oscillator output signal 154 is applied to input of an envelope detector 106 to produce envelope detector output signal 156. Envelope detector output signal 156 is filtered by a low-pass filter 110 to obtain amplitude demodulated output signal 178 which is proportional to the received RF input signal amplitude. Envelope detector output signal 156 is also applied to an amplitude control circuit 108 to produce the amplitude control signal 158, thus performing an automatic oscillator's amplitude level control function (in similar way to an automatic gain control function in a typical super-heterodyne receiver), Amplitude control circuit 108 is responsive to an ACL enable signal 160 which is produced by clock and logic control 122. The oscillator output signal 154 is also applied to input of fixed ratio ECL frequency divider 114 via isolation amplifier 112 (which is inserted between output of voltage controlled oscillator 104 and input of ECL frequency divider 114). ECL frequency divider 114 is enabled by ECL frequency divider enable signal 162 produced by the clock and logic control 122. ECL frequency divider output signal 164 is applied to one of the inputs of a sequential phase comparator 116. Reference frequency signal 166, produced by the clock and logic control 122, is applied to the second input of the sequential phase comparator 116. Sequential phase comparator 116 is enabled by sequential phase comparator enable signal 168, which is produced by the clock and logic control 122. Sequential phase comparator 116 detects phase difference (phase error) between the ECL frequency divider output signal 164 and the reference frequency signal 166. Sequential phase comparator output signal 170 controls operation of a charge pump 118. Charge pump 118 is employed to produce an error signal 172 for the feedback path of the phase-locked loop. Loop filter 120 (in form of at least charge holding capacitor) filters the error signal 172 to produce a frequency control signal 174 (which is applied to frequency control input of the voltage-controlled oscillator 104). Phase-locked loop is enabled only while the quench signal 176 is in logic HIGH state (ON time). When the quench signal 176 is in logic LOW state (OFF time), oscillations are quenched and the voltage at frequency control input of the voltage-controlled oscillator 104 is memorized by the charge holding capacitor of the loop filter 120. During the ON time, phase-locked loop compensates for phase error created during the last OFF time. When turning power on to the circuit, phase-locked loop has to first run in continuous mode until initial frequency acquisition is achieved. That is not desired in certain applications, where power consumption is of concern, and thus it limits the usability of such approach. Addition of the frequency divider, the sequential phase comparator and the charge pump increases complexity, size and cost of the circuit. Since the power consumption of the ECL frequency divider increases with frequency, such approach does not assure the minimal power consumption of the receiver for higher frequencies such as microwaves. Current state of the technology also imposes upper frequency limit where the ECL frequency divider operates reliably.